Many circuit test systems comprise a plurality of test channels, wherein each of the channels is provided with a set of pin electronics that enables the channel to apply stimuli to, or receive responses from, a device under test (DUT). When applying stimuli to a DUT, a set of pin electronics may generate signals in accord with a sequence of test patterns that is specified by a test program. Similarly, and when receiving responses from the DUT, the set of pin electronics may compare DUT responses to a sequence of test patterns specified by the test program.
Given the real-world variances that a test channel may be exposed to as a result of manufacturing variances, environmental conditions and customer loading of the test channel (e.g., via a customer interface or load board that may be coupled to the test channel), a test channel needs to be calibrated. Many types of calibration data may be obtained for a test channel, and the methods and apparatus for obtaining such calibration data are beyond the scope of this disclosure.
Once obtained, calibration data for a test channel may be used, for example, to determine cycle and edge delays that need to be applied to signals that are generated (or received) via the pin electronics of the test channel. Often, a test channel's calibration data is used to construct one or more “timing sets” that are loaded into the pin electronics for the test channel. These timing sets are then used “on-the-fly” to calibrate the signals that are generated (or received) via the pin electronics. Under control of a test program, the pin electronics may be instructed to access different ones of its timing sets when generating or receiving signals having, for example, different cycle times or different signaling levels.